This invention relates to a semiconductor memory device, and more particularly to a semiconductor memory including random accessible dynamic memory cells for which refresh operation is required.
As memories in information processing systems such as work stations or personal computers, etc., Random Access Memories (hereinafter referred to as RAMs) are used.
RAM is roughly classified into Dynamic RAM (DRAM) of which memory content is periodically refreshed and Static RAM (SRAM) for which no refresh operation is required.
In recent years, miniaturization and high integration of devices have been developed. As a result, a system on silicon such that many functional units are mounted on the chip to constitute a system has been put into practice. As an example of such a system on silicon, a microcomputer chip can be mentioned. In the microcomputer chip, a logic unit such as a microprocessor unit (hereinafter referred to as MPU) and a memory unit such as a RAM are mounted on a single chip. In this case, if an approach is employed to pursue high integration equivalent to that of a single chip RAM, additional process technology is required for the portion of the memory cell, so manufacturing cost is increased. For example, in a DRAM, when an attempt is made to provide a higher degree of integration, it is necessary to allow a capacitor of a cell to be of trench/stack structure. On the other hand, when an approach is employed to pursue high integration in an SRAM, high resistance polycrystalline silicon as load element and thin film transistor TFT must be formed. As a result, cost is increased.
It is conceivable to use an SRAM in which the memory cell is comprised of six transistors N111-N116 as shown in FIG. 1. However, since an SRAM has a greater number of elements, it is not suitable for implementation of large capacity.
A RAM using four transistor dynamic memory cells comprised of four transistors is shown in FIG. 2. At the time of access, this memory cell drives a bit line BL and /BL by transistors similarly to an ordinary SRAM. For this reason, access time is short as compared to an ordinary DRAM in which capacitive coupling between the memory cell and bit line is used.
Further, holding of data is carried out by using parasitic capacitance (capacitor) attendant to a node within the memory cell or gate capacitance (capacitor) C and junction capacitance (capacitor). However, by leakage current of transistor for drive or leakage current produced at the junction of diffused layer, potential on the node which has held data is lowered. For this reason, periodical refresh is required similarly to an ordinary DRAM.
In DRAM in which memory cells are each comprised of one (1) transistor N101 and one (1) capacitor Cs, the (potential of) word line WL rises at the time of read-out so that the transistor is activated. Thus, the cell capacitor and bit line capacitor are coupled, so potential on bit line BL is changed. This change of potential is amplified and is read out by a sense amplifier. However, data stored in the memory cell is broken simultaneously with read-out operation. For this reason, it is necessary to use a latch type sense amplifier to allow the bit line to undergo positive feedback so that the amplitude is caused to be large to rewrite data into the memory cell for a second time. Further, it is necessary to carry out a similar read-out operation also at the time of refresh to rewrite data into the memory cell.
On the contrary, in a memory cell of a four (4) transistor type DRAM, potential changes (fluctuates) at the time of read-out, but cell data is not broken. Accordingly, there is no necessity to allow the bit line to undergo positive feedback to rewrite data for a second time.
In this case, refresh of the memory cell can be conducted by activating the word line to charge the memory node which holds data through a transfer transistor. It is unnecessary to activate the sense amplifier or to swing the (amplitude of) potential of the bit line to much degree. Accordingly, refresh time is short and power consumption resulting from charge/discharge of the bit line can be held down to low value.
In addition, as compared to an ordinary SRAM constituting a memory cell with six (6) transistors, a load element is unnecessary. Accordingly, the area is small and implementation of high integration can be therefore made.
However, in the memory cell of a four (4) transistor type DRAM, capacitance of the memory node is smaller than that of an ordinary DRAM. Thus, the refresh cycle is short and it is necessary to frequently carry out refresh. As a result, overhead of the refresh cycle is long, so the mean operation speed is lowered.